1. Field of the Invention
The present invention relates to a method for fabricating a capacitor of a semiconductor device, and more particularly, to a method for fabricating a capacitor of a dynamic random access memory (DRAM), capable of increasing the capacitance of the capacitor.
2. Description of the Prior Art
Generally, an increased integration degree of a semiconductor device such as a DRAM inevitably involves a reduction in the surface area of a unit cell. Such a reduction in the surface area of a unit cell results in a reduction in the unit cell area of the DRAM. In spite of the reduced unit cell area, however, the capacitance of capacitors used for the DRAM should be kept at a value of about 40 famto Farads.
There have been proposed various capacitor structures for obtaining an appropriate capacitance and yet achieving a high integration. Of these capacitor structures, the most representative one is the stack structure.
A DRAM including a capacitor of a conventional stack structure will be described in conjunction with FIG. 5.
The capacitor structure shown in FIG. 5 is fabricated in the following manner. An element isolation film 52 is formed on a portion of a silicon substrate 51 corresponding to a field region. Thereafter, a transistor is formed on a portion of the silicon substrate 51 corresponding to an active region. The transistor includes a gate oxide film 53, a gate electrode 54, and a source/drain electrode 55. Over the element isolation film 52, a word line 54A is formed such that it passes through the field region. Over the entire exposed surface of the resulting structure, an insulating oxide film 57 is formed. Subsequently, the insulating oxide film 57 is partially etched so as to expose a predetermined storage electrode contact region, that is, the source/drain electrode 55. A storage electrode 58 is then formed such that it is in contact with the exposed source/drain electrode 55. Over the storage electrode 58, a dielectric film 59 is then formed. Finally, a plate electrode 60 is formed over the entire exposed surface of the resulting structure. In FIG. 5, the reference numeral 56 denotes insulating film spacers respectively formed on side walls of the gate electrode 54.
In the above-described conventional method, the surface area of the storage electrode is increased by increasing the area of the storage electrode or by increasing the thickness of the storage electrode at edge portions of the storage electrode.
As the DRAM has a much higher integration degree, the above-mentioned simple stack structure obtains an insufficient capacitance.